
2-22 Mechanisms and Operation Rev. A
ROM (2M or 4M bits)
A printer control program and character generator data is written into FLASH ROM (U6). The
control program controls basic printer operations, and all CPU (U4) control is performed in
accordance with this program.
Gate array
The gate array (U5) of this printer controls power to the impact head and thermal head. It is
equipped with four 8-bit I/O ports, PS-RAM controller, and a +24V control time-limit circuit.
The gate array has its own independent 8MHz external clock. The table below shows the
function of each gate array pin.
Gate array signal assignments and functions
No. Pin name Signal name Function I/O Level
1 TEST TEST Connected to GND I TTL
2 RAMCS
RAMCS RAM chip select signal; L: ON I TTL
3GACS
GACS Gate array select signal; L: ON I TTL
4WR
WR Data write signal I TTL
5RD
RD Data read signal I TTL
6PSCE
PSCE PS-RAM (U-7) chip select signal; L: ON O TTL
7 VDD VDD Main power supply terminal (+5V) I (+5V)
8
9
10
11
12
13
14
A6
A5
A4
A3
A2
A1
A0
A6
A5
A4
A3
A2
A1
A0
Address bus I TTL
15 VSS VSS GND terminal I (0V)
16
17
18
19
20
21
22
23
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Data bus 3 state TTL
24 VSS VSS GND terminal I (0V)
25 VDD VDD Main power supply terminal (+5V) I (+5V)
26 PB7 Not used. Open O TTL
27 SW24V_1 Not used. Open O TTL
28 SW24V_2 SW24V2 Printer mechanism +24V time-limit power; H: ON O TTL
29 RTS RTS HOST I/F RTS L:ON O TTL
30 SCLK
CLK IN/DTR HOST I/F CLK IN/DTR I TTL
31 RESET
RESET Reset input; L: ON I -------
32 VSS VSS GND terminal I (0V)
Kommentare zu diesen Handbüchern