Epson LX-86TM Spezifikationen PDF herunterladen (Seite 47)

REV.-A

Functions of the E05A03 gate array (IC3B) are as follows:

1. Address latch

The gate array latches data on address data lines

DBO

DB7

at the leading edge of the ALE signal,

and outputs it to

ABO

AB7

(when ALE is high, the data is passed through without latching.)

2. Address mapping

The gate array inputs an address on AB 13-

——

AB 15, and selects

1 or CS2 or enables the R/W mode

of this gate array using internal decoder 2.

3. Handshaking

● The gate array latches data on

INO

IN7 at the leading edge of the STROBE signal, and automatically

outputs the BUSY signal. The BUSY signal

(DB7)

is latched by the timing register to inform the CPU

that data has been transmitted to the CPU.

● The timing for the BUSY signal, which is set at either the trailing or leading edge of the STROBE

signal, is selected by the control program (firmware).

● The BUSY signal output from the timing register is

wire-ORed with the BUSY signal controlled by

the firmware.

——

.—

Printhead

solenoid drive pulse

. When the FIRE signal from the CPU is brought Low, the data that was previously latched is output

on HD 1

- HD9 to drive the corresponding solenoids in the printhead.

● When FIRE is high,

HDI

- HD9 are all low.

5. Shift register

● This gate array includes a shift register

(8bits X 3), and the MSB (Most Significant Bit) can be read

by accessing the specified address

(XX03H) once. The data is shifted one bit to the left at the leading

edge of the

signal.

6. Initialization

——

When the INIT or

RESI

signal is low, the gate array sets

RESO

low and initializes the following.

●

Printhead

latch (HD 1 - HD9 are all set low even if FIRE is low.)

● PF motor latch (PFA - PFD) are all set low.)

——

● CR motor latch (CRA - CRD) are all set high.)

. Timing generator (enters the state indicating that no data has been received.)

● Control latch (BUSY is set high (software-BUSY), PE is set low, and PELP, NLQLP, and CNDLP are set

high.)

7. Address decoder 2

Address decoder 2 selects one of the twelve modes listed in Table 2-13 according to the combination

of lower address bits OOH - 07H,

and

2-15

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 141 142

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