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REV.-B

Number

.—

Port

~ssignment

ALE

PFO

PF7

PDO

PD7

V DD

Vcc

Table 2-3. CPU Port Assignment (cent’d)

1/0

Signal Line

Name

ALE

[

A 15

DBO

(AO)

DB7

(A7)

—

Description

Memory write timing strobe signal. Connected to the WR

strobe terminal of the gate array and the write enable terminal

of the RAM.

Address latch enable signal. Controls address latching per-

formed inside the gate array (enables latching when the signal

is HIGH).

8-bit 1/0 ports with output latch. Used as the upper address

bus according to the MODE 0/1 terminal selection. For 64K

external memory assignment), Al 3 through Al 5 are input to

the address decoder in the gate array.

Multiplexed

addressldata bus. Used as the lower address and

data bus.

Power supply for the internal RAM (+5

VDC).

.—

Power supply for the CPU

(+5

VDC).

When this voltage is not

stable, such as at either a leading or trailing edge (when the

printer power is turned on or off), the reset circuit prevents the

CPU from running.

NOTES: 1. All barred signal are LOW active.

2. “1/0” denotes either input or output when viewing the signal from the CPU.

2-13

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