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112 EPSON S1C63466 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
Item
SVD voltage
SVD voltage (external) ∗4
SVD circuit response time
Current consumption
∗1
∗2
∗3
∗4
Symbol
VSVD1
VSVD2
tSVD
IOP
Unit
V
V
µs
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Max.
Typ.
×1.07
1.15
100
2
12
8
45
60
50
19
80
800
1,400
1,000
7
3
Typ.
1.85
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
1.05
1
6
4
23
30
26
10
45
600
1,200
800
Min.
Typ.
×0.93
0.95
1
0.5
Without panel load. The SVD circuit is OFF.
VDC = "0"
OSCC = "0"
Please input the voltage, which is within the range between V
SS and VDD, into the SVD terminal.
Condition
SVDS0–3="0" (internal)
SVDS0–3="1"
SVDS0–3="2"
SVDS0–3="3"
SVDS0–3="4"
SVDS0–3="5"
SVDS0–3="6"
SVDS0–3="7"
SVDS0–3="8"
SVDS0–3="9"
SVDS0–3="10"
SVDS0–3="11"
SVDS0–3="12"
SVDS0–3="13"
SVDS0–3="14"
SVDS0–3="15"
SVDS0–3="0" (external)
During HALT (32 kHz crystal oscillation),
LCD power OFF ∗1, ∗2, ∗3
During HALT (32 kHz crystal oscillation),
LCD power ON (
VC1 standard
) ∗1, ∗2, ∗3
During HALT (32 kHz crystal oscillation),
LCD power ON (
VC2 standard
) ∗1, ∗2, ∗3
During HALT (60 kHz CR oscillation),
LCD power OFF ∗1, ∗3
During HALT (60 kHz CR oscillation),
LCD power ON (
VC1 standard
) ∗1, ∗3
During HALT (60 kHz CR oscillation),
LCD power ON (
VC2 standard
) ∗1, ∗3
During execution (32 kHz crystal oscillation),
LCD power ON (
VC1 standard
) ∗1, ∗2, ∗3
During execution (60 kHz CR oscillation),
LCD power ON (
VC1 standard
) ∗1, ∗3
During execution (2 MHz ceramic oscillation),
LCD power ON (
VC1 standard
) ∗1
During execution (4 MHz ceramic oscillation),
LCD power ON (
VC1 standard
) ∗1
During execution (1,800 kHz CR oscillation),
LCD power ON (
VC1 standard
) ∗1
SVD circuit current (during supply voltage detection)
VDD=1.85 to 6.4 V
SVD circuit current (during external voltage detection)
VDD=1.85 to 6.4 V
Unless otherwise specified:
VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, RCR1=600kΩ, RCR2=47kΩ, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage,
C1–C8=0.2µF
- S1C63466 1
- CONTENTS 7
- EPSON iii 9
- 1OUTLINE 11
- 1.2 Block Diagram 12
- 1.3 Pin Layout Diagram 13
- 1.4 Pin Description 15
- 1.5 Mask Option 16
- CHAPTER 1: OUTLINE 17
- 2.1 Power Supply 19
- 2.2 Initial Reset 21
- 2.3 Test Terminal (TEST) 23
- 3 CPU, ROM, RAM 24
- 3.4 Data ROM 25
- CHAPTER 4 26
- ERIPHERAL 26
- PERATION 26
- ∗2 Not set in the circuit 27
- EPSON 19 29
- EPSON 21 31
- 4.2 Watchdog Timer 32
- 4.2.4 Programming notes 33
- 4.3 Oscillation Circuit 34
- (sound quality) 35
- EPSON 27 37
- 4.3.7 Programming notes 38
- 4.4.2 Interrupt function 39
- 4.4.3 Mask option 40
- EPSON 31 41
- 4.4.5 Programming notes 43
- 4.5.2 Mask option 44
- 4.5.3 High impedance control 45
- 4.5.4 Special output 45
- •TOUT (R02) 46
- • FOUT (R03) 46
- EPSON 37 47
- 4.5.6 Programming notes 49
- 4.6.2 Mask option 51
- 4.6.6 I/O memory of I/O ports 53
- (2) I/O port control 55
- 4.6.7 Programming notes 56
- EPSON 47 57
- 4.7.3 Mask option 58
- EPSON 49 59
- 4.7.5 Display memory 61
- 4.7.6 LCD contrast adjustment 62
- EPSON 53 63
- 4.7.8 Programming notes 65
- 4.8 Clock Timer 66
- 4.8.3 Interrupt function 67
- EPSON 59 69
- 4.8.5 Programming notes 70
- 4.9 Stopwatch Timer 71
- 4.9.3 Interrupt function 72
- EPSON 63 73
- 4.9.5 Programming notes 74
- 4.10 Programmable Timer 75
- 4.10.3 Counter mode 77
- (1) Selection of source clock 78
- Timer 1 underflow 80
- Source clock for serial I/F 80
- EPSON 71 81
- EPSON 73 83
- EPSON 75 85
- 4.10.9 Programming notes 86
- EPSON 77 87
- 4.11.2 Mask option 88
- EPSON 79 89
- SD3 SD2 SD1 SD0 90
- SD4 SD5 SD6 SD7 90
- SD7 SD6 SD5 SD4 90
- SD0 SD1 SD2 SD3 90
- (5) Timing chart 91
- EPSON 83 93
- SS) level 94
- DD) level bit 94
- 4.11.6 Programming notes 95
- 4.12 Sound Generator 96
- 4.12.6 One-shot output 99
- *2 Not set in the circuit 100
- EPSON 91 101
- 4.12.8 Programming notes 102
- Data bus 103
- 4.13.5 Programming notes 105
- 4.14 Interrupt and HALT 106
- EPSON 97 107
- 4.14.1 Interrupt factor 108
- EPSON 99 109
- EPSON 101 111
- 4.14.5 Programming notes 112
- 5SUMMARY OF NOTES 113
- Memory and stack 114
- Watchdog timer 114
- Oscillation circuit 114
- Input port 115
- Output port 115
- I/O port 115
- LCD driver 115
- Clock timer 115
- Stopwatch timer 116
- Programmable timer 116
- Serial interface 116
- Sound generator 117
- SVD circuit 117
- Interrupt 117
- 7ELECTRICAL CHARACTERISTICS 119
- 7.3 DC Characteristics 120
- CR oscillation frequency f 124
- <Master mode> 125
- <Slave mode> 125
- 2.5 msec min 126
- 5 msec min 126
- CHAPTER 8PACKAGE 127
- QFP17-144pin 128
- QFP5-128pin 129
- QFP8-144pin 130
- CHAPTER 9PAD LAYOUT 133
- CHAPTER 9: PAD LAYOUT 134
- APPENDIX S5U1C63000P MANUAL 135
- OSC1 rough adjustment 136
- OSC1 fine adjustment 136
- OSC3 rough adjustment 136
- OSC3 fine adjustment 136
- (7) RESET switch 137
- (9) IOSEL2 137
- (10) CLK and PRG switch 137
- (11) VC5 137
- I/O connection cable 138
- To target board 138
- A.3 Usage Precautions 140
- (3) Functional precautions 141
- First issue July, 1998 144
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