Epson ARM.POWERED ARM720T Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Hardware Epson ARM.POWERED ARM720T.
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Epson ARM.POWERED ARM720T Bedienungsanleitung (224 Seiten)

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Inhaltsverzeichnis

ARM720T Revision 4

Contents

7 Memory Management Unit

List of Figures

List of Tables

CONTENTS

About this document

Typographical conventions

Product revision status

AMBA Specification (Rev 2.0)

Introduction

1 Introduction

1: Introduction

1.1.1 EmbeddedICE-RT logic

1.2 Coprocessors

1.3 About the instruction set

1.3.1 Format summary

1.3.2 ARM instruction set

Table 1-3 Addressing mode 2

Table 1-11 Condition fields

1.3.3 Thumb instruction set

1.4 Silicon revisions

Programmer’s Model

2 Programmer’s Model

2.2 Memory formats

2.3 Instruction length

2.4 Data types

2.5 Operating modes

2.6 Registers

2: Programmer’s Model

Stack Pointer

Link Register

2.7 Program status registers

2.7.3 Reserved bits

2.8 Exceptions

2.8.4 Fast interrupt request

2.8.5 Interrupt request

2.8.6 Abort

2.8.7 Software interrupt

2.8.8 Undefined instruction

2.8.9 Exception vectors

2.8.10 Exception priorities

2.8.11 Exception restrictions

Fast Context Switch Extension

Process IDentifier

2.10 Reset

2.11.2 Early termination

Configuration

3 Configuration

3: Configuration

3.3 Registers

3.3.2 Control Register

3.3.5 Fault Status Register

3.3.6 Fault Address Register

3.3.8 TLB Operations Register

3.3.10 Register 14, reserved

3.3.11 Test Register

Instruction and

Data Cache

4 Instruction and Data Cache

4.2 IDC validity

Write Buffer

5 Write Buffer

5.2 Write buffer operation

The Bus Interface

6 The Bus Interface

Address and control signals

AMBA Specification (Rev

6.2 Bus interface signals

6: The Bus Interface

6.3 Transfer types

6.4.1 HADDR[31:0]

6.4.2 HWRITE

6.4.3 HSIZE[2:0]

6.4.4 HBURST[2:0]

6.4.5 HPROT[3:0]

6.5.1 HREADY

6.6 Data buses

6.6.2 HRDATA[31:0]

6.6.3 Endianness

6.7 Arbitration

6.8 Bus clocking

6.9 Reset

Memory Management

7.1.2 Translated entries

7.3 Address translation

100

Level one fetch

101

Level two fetch

101

7.3.2 Level one fetch

102

7.3.3 Level one descriptor

102

7: Memory Management Unit

103

7.3.4 Section descriptor

104

7.3.8 Level two descriptor

106

Table indexTranslation base

108

7.3.12 Subpages

110

7.4 MMU faults and CPU aborts

111

7.5.1 Fault Status

112

7.6 Domain access control

113

Access Permission

114

7.7 Fault checking sequence

115

7.7.2 Translation fault

116

7.7.3 Domain fault

116

7.7.4 Permission fault

116

7.8 External aborts

117

THIS PAGE IS BLANK

118

Coprocessor Interface

119

8 Coprocessor Interface

121

8: Coprocessor Interface

122

8.4.1 The coprocessor

125

8.4.2 The ARM720T core

125

8.4.3 Coprocessor signaling

126

8.5 Connecting coprocessors

129

8.7 STC operations

130

8.8 Undefined instructions

130

8.9 Privileged instructions

130

Debugging Your System

131

9 Debugging Your System

133

9.1.1 A typical debug system

134

9.2 Controlling debugging

135

9.2.1 Debug modes

136

9.3 Entry into debug state

137

9: Debugging Your System

138

Programming breakpoints

139

Programming watchpoints

139

9.3.5 Clocks

140

9.4 Debug interface

141

Watchpoint unit registers

142

9.7 Disabling EmbeddedICE-RT

143

9.9 Monitor mode debugging

144

Abort status register

145

Debug control register

145

Debug Communication Channel

146

Communications through the

146

Test Access Port

149

Boundary-Scan Architecture

149

Test data registers

149

Instruction register

150

The TAP controller

150

9.12 The TAP controller

151

9.13 Public JTAG instructions

152

9.13.3 IDCODE (b1110)

153

9.13.4 BYPASS (b1111)

153

9.13.5 RESTART (b0100)

153

9.14 Test data registers

154

9.14.3 Instruction register

155

9.14.5 Scan chains 1 and 2

156

9.15 Scan timing

157

Debug status register

160

Exit from debug state

160

9.17 Exit from debug state

161

9.18.1 Breakpoints

162

9.18.2 Watchpoints

162

9.18.4 Debug request

163

9.18.5 System speed access

163

Interrupts

164

Data Aborts

164

9.19.2 Interrupts

165

9.19.3 Data Aborts

165

8 67 5 34 2 01

167

9.21 Programming breakpoints

168

9.21.2 Software breakpoints

169

9.22 Programming watchpoints

170

9.23 Abort status register

170

9.24 Debug control register

171

9.24.1 Disabling interrupts

172

9.24.2 Forcing DBGRQ

172

9.24.3 Forcing DBGACK

172

9.25 Debug status register

173

9.27 EmbeddedICE-RT timing

176

ETM Interface

177

10 ETM Interface

179

ARM720T processor

180

10.4 Clocks and resets

181

10.5 Debug request wiring

181

10.6 TAP interface wiring

181

Test Support

183

11 Test Support

185

11: Test Support

186

11.3 Test State Register

187

Translation Table Base

192

Domain Access Control

192

Fault Status Register

192

Fault Address Register

192

31 654 0

194

MVA TAG V P

194

SBZSIZE_C

194

Base SBZ

196

2526 20 19 1

196

Appendix A

199

Signal Descriptions

199

A Signal Descriptions

201

A: Signal Descriptions

202

A.3 JTAG and test signals

203

A.4 Debugger signals

204

A.6 ATPG test signals

207

A.7 Miscellaneous signals

207

Glossary

209

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Epson ARM.POWERED ARM720T Handbücher

Epson ARM.POWERED ARM720T Bedienungsanleitung (224 Seiten)

Inhaltsverzeichnis

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