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S-MOS SYSTEMS, INC.
1.0 Overview 1.3
1.3 Block Diagram
LINE ADDRESS DECODER
DISPLAY DATA RAM
2560 BITS
I/O BUFFER
INTERNAL BUS
LOW ADDRESS
REGISTER
BUS
HOLDER
LINE COUNTER
DISPLAY
TIMING
GENERATOR
DISPLAY START LINE REGISTER
FR
COMMAND
DECODER
COLUMN ADDRESS REGISTER
STATUS
MPU INTERFACE
COLUMN ADDRESS COUNTER
COLUMN ADDRESS DECODER
DISPLAY DATA LATCH CIRCUIT
LCD DRIVER CIRCUIT
COMMON
COUNTER
CL
(OSC2)
D0 ~ D7
E , R/W
(OSC1)
RES
(RD)(WR)
V
DD
V
SS
V1, V4, M/S
(SG77 ~ SG79)
(SG61 ~ SG76)
SG0 ~ SG60
CM0 ~ CM15
V2, V3, V5
A0, CS
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