Epson S1C6200A Spezifikationen PDF herunterladen (Seite 122)

I-110 EPSON S1C62740 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)

Interrupt vector

When an interrupt request is input to the CPU, the CPU begins

interrupt processing. After the program being executed is termi-

nated, the interrupt processing is executed in the following order.

➀ The address data (value of program counter) of the program to

be executed next is saved in the stack area (RAM).

➁ The interrupt request causes the value of the interrupt vector

(page 1, 02H–0FH) to be set in the program counter.

➂ The program at the specified address is executed (execution of

interrupt processing routine by software).

Table 4.15.3 shows the correspondence of interrupt requests and

interrupt vectors.

Note: The processing in

➀

and

➁

above take 12 cycles of the CPU system clock.

Table 4.15.3

Interrupt request and interrupt

vectors

The four low-order bits of the program counter are indirectly

addressed through the interrupt request.

Interrupt vector Interrupt request Priority

102H Clock timer Low

104H Stopwatch timer ↑

106H A/D converter

108H K00–K03 input

10AH K10 input

10CH Serial interface ↓

10EH Programmable timer High

1 2 ... 117 118 119 120 121 122 123 124 125 126 127 ... 248 249

Keine Kommentare

Epson S1C6200A Spezifikationen Seite 122