Epson S1C33 Spezifikationen

MF1359-02ASIC DESIGN GUIDECMOS 32-BIT SINGLE CHIP MICROCOMPUTER Embedded Array S1X50000 SeriesS1C33

1 Product Overview4EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES(*) SNRC: Net list rule checkerTable 1.1 Work Involved in Each Step of

1 Product OverviewS1C33 ASIC DESIGN GUIDEEPSON5EMBEDDED ARRAY S1X50000 SERIESFigure 1.2 Division of Responsibility in the Development Process

1 Product Overview6EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESES (engineering sample) productionQualification of mass productionFuncti

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON7EMBEDDED ARRAY S1X50000 SERIESChapter 2 C33 Macro Specifications2.1 OverviewThe C33 macro mode

2 C33 Macro Specifications8EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2.2 Block DiagramFigure 2.1 C33 Macro Block DiagramTerminologyB

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON9EMBEDDED ARRAY S1X50000 SERIESSBUS: Bus control block that has an address/data bus structure c

2 C33 Macro Specifications10EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2.3 C33 Macro Pins(1) C33 Macro - Required pins (pad connection

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON11EMBEDDED ARRAY S1X50000 SERIES(2) C33 Macro - Optional pins (pad connections) (12 pins)Table

2 C33 Macro Specifications12EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES(3) C33 Macro - Peripheral function pins (pad connections) (44

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON13EMBEDDED ARRAY S1X50000 SERIES(*) Pins P_P10 to P_P14 are used as S5U1C33000H interface pins.

NOTICENo part of this material may be reproduced or duplicated in any form or by any means without the writtenpermission of Seiko Epson. Seiko Epson r

2 C33 Macro Specifications14EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESTable 2.3.5 User Logic Interface PinsConnection: User logicPin

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON15EMBEDDED ARRAY S1X50000 SERIES2.4 Special SignalsThe U_BUSSZ[1:0] and U_BUSMD[2:0] signals in

2 C33 Macro Specifications16EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESThe U_RST_X signal outputs the value of the P_RESETX pad pin sh

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON17EMBEDDED ARRAY S1X50000 SERIES2.6 Electrical CharacteristicsThe C33 macro I/O cell library is

2 C33 Macro Specifications18EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2.6.2 Recommended Operating Conditions1) 3.3V single power sour

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON19EMBEDDED ARRAY S1X50000 SERIES3) 3.3 V/5.0 V dual power source(VSS=0V)*1: Either 5.25 V or 5.

2 C33 Macro Specifications20EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2.6.3 DC Characteristics1) 3.3V/5.0V dual power source (Unless

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON21EMBEDDED ARRAY S1X50000 SERIES3) 2.0V single power source(Unless otherwise specified: VDD=1.

2 C33 Macro Specifications22EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2) 2.0V single power source (Unless otherwise specified: VDD=1

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON23EMBEDDED ARRAY S1X50000 SERIES2) 3.3V single power source(Unless otherwise specified: VDD=AVD

The information of the product number changeConfiguration of product numberDevicesComparison table between new and previous numberS1C33 Family process

2 C33 Macro Specifications24EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2.6.6 AC CharacteristicsThe C33 macro block AC characteristics

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON25EMBEDDED ARRAY S1X50000 SERIES2.6.6.1 Symbol DescriptiontCYC: Bus-clock cycle time• In x1 mo

2 C33 Macro Specifications26EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2.6.6.2 AC Characteristics Measurement ConditionSignal detectio

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON27EMBEDDED ARRAY S1X50000 SERIES2.6.6.3 AC Characteristics Tables (I/O Buffer Pins)The tables i

2 C33 Macro Specifications28EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESBCLK clock output chracteristicsNote: These AC characteristic

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON29EMBEDDED ARRAY S1X50000 SERIES2) 3.3V single power source(Unless otherwise specified: VDD=2.

2 C33 Macro Specifications30EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES2) 3.3V single power source(Unless otherwise specified: VDD=2.7

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON31EMBEDDED ARRAY S1X50000 SERIESDRAM access cycle common characteristicsThe #RAS and #CAS symbo

2 C33 Macro Specifications32EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES3) 2.0V single power source(Unless otherwise specified: VDD=1.8

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON33EMBEDDED ARRAY S1X50000 SERIESEDO DRAM random access cycle and EDO DRAM page cycle1) 3.3V/5.0

2 C33 Macro Specifications34EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESBurst ROM read cycle1) 3.3V/5.0V dual power source(Unless other

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON35EMBEDDED ARRAY S1X50000 SERIES1) 3.3V/5.0V dual power source(Unless otherwise specified: HVDD

2 C33 Macro Specifications36EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESInput, Output and I/O portThe tables in this section stipulate

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON37EMBEDDED ARRAY S1X50000 SERIES2.6.6.4 AC Characteristics Timing Charts (I/O Buffer Pins)This

2 C33 Macro Specifications38EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESSRAM read cycle (when a wait cycle is inserted)∗1tRDH is measur

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON39EMBEDDED ARRAY S1X50000 SERIESSRAM write cycle (when wait cycles are inserted)DRAM random acc

2 C33 Macro Specifications40EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESDRAM fast-page access cycle∗1tRDH is measured with respect to t

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON41EMBEDDED ARRAY S1X50000 SERIESEDO DRAM page access cycle∗1tRDH is measured with respect to th

2 C33 Macro Specifications42EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESBurst ROM read cycle∗1tRDH is measured with respect to the firs

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON43EMBEDDED ARRAY S1X50000 SERIES2.6.6.5 AC Characteristics Tables (User Logic Interface)The tab

ContentsS1C33 ASIC DESIGN GUIDE EPSONiEMBEDDED ARRAY S1X50000 SERIESContentsChapter 1 Product Overview ...

2 C33 Macro Specifications44EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESCommon Characteristics (User Logic Interface)The VDD and VSS le

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON45EMBEDDED ARRAY S1X50000 SERIES2.6.6.6 AC Characteristics Timing Charts (User Logic Interface)

2 C33 Macro Specifications46EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESResetSRAM read cycle (Basic cycle: 1 cycle)∗1tRDH is measured w

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON47EMBEDDED ARRAY S1X50000 SERIESSRAM read cycle (when a wait cycle is inserted)∗1tRDH is measur

2 C33 Macro Specifications48EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESSRAM write cycle (when wait cycles are inserted)Input, output a

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON49EMBEDDED ARRAY S1X50000 SERIES2.6.6.7 Oscillation CharacteristicsOscillation characteristics

2 C33 Macro Specifications50EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESOSC3 crystal oscillationNote: A "crystal resonator that us

2 C33 Macro SpecificationsS1C33 ASIC DESIGN GUIDEEPSON51EMBEDDED ARRAY S1X50000 SERIES2.6.6.8 PLL CharacteristicsSetting the PLLS0 and PLLS1 pins (re

3 C33 Test Functions52EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESChapter 3 C33 Test Functions3.1 Test Function OverviewThe C33 macro

3 C33 Test FunctionsS1C33 ASIC DESIGN GUIDEEPSON53EMBEDDED ARRAY S1X50000 SERIES3.2 DC/AC Test Mode (TST_DCT mode)3.2.1 Procedure to Enter Test Mod

ContentsiiEPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESChapter 4 Special Operations in ASICs that Include C33 Macros ... 624.1 Special

3 C33 Test Functions54EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES3.2.2 Test ModeIn the DC/AC test mode, the user I/O cells are control

3 C33 Test FunctionsS1C33 ASIC DESIGN GUIDEEPSON55EMBEDDED ARRAY S1X50000 SERIES3) Input logic level verification modeP_X2SPDX (IP0) ... Fixed at the

3 C33 Test Functions56EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES$PATTERN# PPPPPPPPPPPPPPPPPPPPPPPPBOO# ________________________IUU# R

3 C33 Test FunctionsS1C33 ASIC DESIGN GUIDEEPSON57EMBEDDED ARRAY S1X50000 SERIES108 111P11L000000000000000000ZH Since this example is the result of s

3 C33 Test Functions58EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESFigure 3.2 Sample Pattern WaveformsGroup: AP_OSC3 = XP_TST = 0

3 C33 Test FunctionsS1C33 ASIC DESIGN GUIDEEPSON59EMBEDDED ARRAY S1X50000 SERIES3.3 User Circuit Test Mode (TST_USER mode)3.3.1 Procedure to Enter

3 C33 Test Functions60EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES3.3.2 Test ModeIn user circuit test mode, the clock, address, data, r

3 C33 Test FunctionsS1C33 ASIC DESIGN GUIDEEPSON61EMBEDDED ARRAY S1X50000 SERIESCaution: Provide the chip enable signal to the user circuit as shown

4 Special Operations in ASICs that Include C33 Macros62EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESChapter 4 Special Operations in ASI

4 Special Operations in ASICs that Include C33 MacrosS1C33 ASIC DESIGN GUIDE EPSON63EMBEDDED ARRAY S1X50000 SERIES4.3 Verifying the Constraints on th

1 Product OverviewS1C33 ASIC DESIGN GUIDEEPSON1EMBEDDED ARRAY S1X50000 SERIESChapter 1 Product Overview1.1 IntroductionThis product, abbreviated here

4 Special Operations in ASICs that Include C33 Macros64EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESFigure 4.1 Sample Floorplan and Pin

4 Special Operations in ASICs that Include C33 MacrosS1C33 ASIC DESIGN GUIDE EPSON65EMBEDDED ARRAY S1X50000 SERIES4.4 Connections between User I/O,

4 Special Operations in ASICs that Include C33 Macros66EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES4.4.4 Connections between C33 Macro

4 Special Operations in ASICs that Include C33 MacrosS1C33 ASIC DESIGN GUIDE EPSON67EMBEDDED ARRAY S1X50000 SERIES4.5 Test Pattern Creation4.5.1 DC/A

5 Simulation68EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY SSL50000 SERIESChapter 5 Simulation5.1 Design FlowchartFigure 5.1 Design FlowchartBulk Desi

5 SimulationS1C33 ASIC DESIGN GUIDEEPSON69EMBEDDED ARRAY S1X50000 SERIESFigure 5.2 Simulation FlowchartNote: Current there is only a gate level simu

5 Simulation70EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY SSL50000 SERIES5.2 System Level SimulationFigure 5.3 System Level Simulation5.3 Test Patter

5 SimulationS1C33 ASIC DESIGN GUIDEEPSON71EMBEDDED ARRAY S1X50000 SERIES5.4 Simulation Environment5.4.1 Operating EnvironmentThe standard simulation

5 Simulation72EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY SSL50000 SERIESThe C33 macro net list consists of the hard macros, the soft macros, and the

5 SimulationS1C33 ASIC DESIGN GUIDEEPSON73EMBEDDED ARRAY S1X50000 SERIES5.5.3 Simulation Execution ScriptThe C33 simulation is executed by the follow

1 Product Overview2EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES• Other features: Little endian (Certain areas can be set up for big en

5 Simulation74EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY SSL50000 SERIES Example 1) Normal simulationcsh> c33_sim.csh sample.asm trc=test1 tcyc=1

5 SimulationS1C33 ASIC DESIGN GUIDEEPSON75EMBEDDED ARRAY S1X50000 SERIEScsh> grep //_ _ samplex_f10emux1.tb//_ _.../sim/verilog/ENV/tb/header.tb

5 Simulation76EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY SSL50000 SERIES5.6 Evaluation Program Creation5.6.1 asm33 Assembler PrototypeThe procedure f

5 SimulationS1C33 ASIC DESIGN GUIDEEPSON77EMBEDDED ARRAY S1X50000 SERIES(2) Limitations on registers, values, and labels• Character setThere are 3 de

5 Simulation78EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY SSL50000 SERIES5) Jump instructions that require an immediate value extended instruction mus

6 Board DevelopmentS1C33 ASIC DESIGN GUIDEEPSON79EMBEDDED ARRAY S1X50000 SERIESChapter 6 Board Development6.1 Development EnvironmentFigure 6.1 S1C3

6 Board Development80EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES• Host computer• Personal computer running Windows 95, 98, or NT• Soft

6 Board DevelopmentS1C33 ASIC DESIGN GUIDEEPSON81EMBEDDED ARRAY S1X50000 SERIESFigure 6.2 S5U1C33XXE QFP InterfaceUser target boardFor mass producti

6 Board Development82EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES6.2 Evaluation Board DesignFigure 6.3 Board Development FlowchartDete

6 Board DevelopmentS1C33 ASIC DESIGN GUIDEEPSON83EMBEDDED ARRAY S1X50000 SERIES(1) Board development process (example 1)Step 1: Determine the C33 ASI

1 Product OverviewS1C33 ASIC DESIGN GUIDEEPSON3EMBEDDED ARRAY S1X50000 SERIES1.2 Interface and Design Process FlowchartFigure 1.1 Total Product Deve

6 Board Development84EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIES(2) Board development process (example 2)Use the following procedure w

7 MountingS1C33 ASIC DESIGN GUIDEEPSON85EMBEDDED ARRAY S1X50000 SERIESChapter 7 Mounting7.1 Precautions on MountingThe following shows the precaution

7 Mounting86EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESReset Circuit • The power-on reset signal which is input to the P_RESETX pin ch

7 MountingS1C33 ASIC DESIGN GUIDEEPSON87EMBEDDED ARRAY S1X50000 SERIESRecommended CircuitCG2C1R1*1C23.3VCD2Rf2CG1CD1Rf1X`tal2or CRX`tal1A[23:0]D[23:0

7 Mounting88EPSONS1C33 ASIC DESIGN GUIDEEMBEDDED ARRAY S1X50000 SERIESArrangement of Signal Lines• In order to prevent generation of electromagnetic

7 MountingS1C33 ASIC DESIGN GUIDEEPSON89EMBEDDED ARRAY S1X50000 SERIES7.2 OthersThe positions (layout) of the following pins is extremely important t

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ASIC DESIGN GUIDES1C33ELECTRONIC DEVICES MARKETING DIVISIONhttp://www.epson.co.jp/device/First issue November, 2000 Printed March, 2001 in Ja