Epson S1C63000 Bedienungsanleitung

Core CPU ManualCMOS 4-BIT SINGLE CHIP MICROCOMPUTERS1C63000MF855-03a

4 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTURECHAPTER 2ARCHITECTUREThis chapter explains the S1C63000 ALU, registers, configuration of the pr

94 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETINC %spINT imm6 Software interrupt 3 cyclesFunction: [SP2-1] ← F, SP2 ← SP2 - 1, ([(SP1-1

S1C63000 CORE CPU MANUAL EPSON 95CHAPTER 4: INSTRUCTION SETJP %Y Indirect jump using Y reg. 1 cycleFunction: PC ← YLoads the content of the Y registe

96 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETJR %BA Jump to relative location BA reg. 1 cycleFunction: PC ← PC + BA + 1Adds the content

S1C63000 CORE CPU MANUAL EPSON 97CHAPTER 4: INSTRUCTION SETJR sign8 Jump to relative location sign8 1 cycleFunction: PC ← PC + sign8 + 1 (sign8 = -12

98 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETJRNC sign8 Jump to relative location sign8 if C flag is reset 1 cycleFunction: If C = 0 th

S1C63000 CORE CPU MANUAL EPSON 99CHAPTER 4: INSTRUCTION SETJRZ sign8 Jump to relative location sign8 if Z flag is set 1 cycleFunction: If Z = 1 then

100 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETLD %r,imm4 Load immediate data imm4 into r reg. 1 cycleFunction: r ← imm4Loads the 4-bit

S1C63000 CORE CPU MANUAL EPSON 101CHAPTER 4: INSTRUCTION SETLD %r,[%ir]+ Load location [ir reg.] into r reg. and increment ir reg. 1 cycleFunction: r

102 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETLD [%ir]+,%r Load r reg. into location [ir reg.] and increment ir reg. 1 cycleFunction: [

S1C63000 CORE CPU MANUAL EPSON 103CHAPTER 4: INSTRUCTION SETLD [%ir]+,imm4Load immediate data imm4 into location [ir reg.] and increment ir reg. 1 cy

S1C63000 CORE CPU MANUAL EPSON 5CHAPTER 2: ARCHITECTURE • A and B registersThe A and B registers are respective 4-bit data registers that are used fo

104 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETLD [%ir],[%ir’]+Load location [ir’ reg.] into location [ir reg.] and increment ir’ reg. 2

S1C63000 CORE CPU MANUAL EPSON 105CHAPTER 4: INSTRUCTION SETLD [%ir]+,[%ir’]+Load location [ir’ reg.] into location [ir reg.] and increment ir and ir

106 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETLDB %BA,[%ir]+ Load location [ir reg.] into BA reg. and increment ir reg. 2 cyclesFunctio

S1C63000 CORE CPU MANUAL EPSON 107CHAPTER 4: INSTRUCTION SETLDB %BA,%rr Load rr reg. into BA reg. 1 cycleFunction: BA ← rrLoads the content of the rr

108 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETLDB [%ir]+,%BA Load BA reg. into location [ir reg.] and increment ir reg. 2 cyclesFunctio

S1C63000 CORE CPU MANUAL EPSON 109CHAPTER 4: INSTRUCTION SETLDB %EXT,imm8 Load immediate data imm8 into EXT reg. 1 cycleFunction: EXT ← imm8Loads the

110 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETLDB %rr,imm8 Load immediate data imm8 into rr reg. 1 cycleFunction: rr ← imm8Loads the 8-

S1C63000 CORE CPU MANUAL EPSON 111CHAPTER 4: INSTRUCTION SETLDB %sp,%BA Load BA reg. into stack pointer 1 cycleFunction: sp ← BALoads the content of

112 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETOR %r,%r’OR %r,imm4Logical OR of r’ reg. and r reg. 1 cycleFunction: r ← r ∨ r’Performs

S1C63000 CORE CPU MANUAL EPSON 113CHAPTER 4: INSTRUCTION SETOR %F,imm4 Logical OR of immediate data imm4 and F reg. 1 cycleFunction: F ← F ∨ imm4Perf

6 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTUREShift/Rotate instructions that change the Z flag:SLL, SRL, RL, RRThe Z flag is used for conditi

114 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETOR %r,[%ir]+ Logical OR of location [ir reg.] and r reg. and increment ir reg. 1 cycleFun

S1C63000 CORE CPU MANUAL EPSON 115CHAPTER 4: INSTRUCTION SETOR [%ir]+,%r Logical OR of r reg. and location [ir reg.] and increment ir reg. 2 cyclesFu

116 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETOR [%ir]+,imm4Logical OR of immediate data imm4 and location [ir reg.] and increment ir r

S1C63000 CORE CPU MANUAL EPSON 117CHAPTER 4: INSTRUCTION SETPOP %irPUSH %r Push r reg. onto stack 1 cycleFunction: [SP2-1] ← r, SP2 ← SP2 -1Decremen

118 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETPUSH %ir Push ir reg. onto stack 1 cycleFunction: ([(SP1-1)*4+3]~[(SP1-1)*4]) ← ir, SP1 ←

S1C63000 CORE CPU MANUAL EPSON 119CHAPTER 4: INSTRUCTION SETRETD imm8 Return from subroutine and load imm8 into location [X] 3 cyclesFunction: PC ← (

120 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETRETSRL %r Rotate left r reg. with carry 1 cycleFunction:Rotates the content of the r regi

S1C63000 CORE CPU MANUAL EPSON 121CHAPTER 4: INSTRUCTION SETRL [%ir] Rotate left location [ir reg.] with carry 2 cyclesFunction:Rotates the content o

122 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETRR %rRR [%ir]Rotate right r reg. with carry 1 cycleFunction:Rotates the content of the r

S1C63000 CORE CPU MANUAL EPSON 123CHAPTER 4: INSTRUCTION SETRR [%ir]+ Rotate right location [ir reg.] with carry and increment ir reg. 2 cyclesFuncti

S1C63000 CORE CPU MANUAL EPSON 7CHAPTER 2: ARCHITECTURE2.1.4 Arithmetic operations with numbering systemIn the S1C63000, some instructions support a n

124 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSBC %r,imm4 Subtract with carry immediate data imm4 from r reg. 1 cycleFunction: r ← r -

S1C63000 CORE CPU MANUAL EPSON 125CHAPTER 4: INSTRUCTION SETSBC %r,[%ir]+Subtract with carry location [ir reg.] from r reg. and increment ir reg. 1 c

126 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSBC [%ir]+,%rSubtract with carry r reg. from location [ir reg.] and increment ir reg. 2 c

S1C63000 CORE CPU MANUAL EPSON 127CHAPTER 4: INSTRUCTION SETSBC [%ir]+,imm4Subtract with carry immediate data imm4 from location [ir reg.] and increm

128 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSBC %B,[%ir],n4 Subtract with carry location [ir reg.] from B reg. in specified radix 2 c

S1C63000 CORE CPU MANUAL EPSON 129CHAPTER 4: INSTRUCTION SETSBC [%ir],%B,n4 Subtract with carry B reg. from location [ir reg.] in specified radix 2 c

130 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSBC [%ir],0,n4 Subtract carry from location [ir reg.] in specified radix 2 cyclesFunction

S1C63000 CORE CPU MANUAL EPSON 131CHAPTER 4: INSTRUCTION SETSET [addr6],imm2 Set bit imm2 in location [addr6] 2 cyclesFunction: [addr6] ← [addr6] ∨ (

132 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSLL [%ir]SLL [%ir]+ Shift left location [ir reg.] logical and increment ir reg. 2 cycles

S1C63000 CORE CPU MANUAL EPSON 133CHAPTER 4: INSTRUCTION SETSLP Set CPU to SLEEP mode 2 cyclesFunction: SleepSets the CPU to SLEEP status.The CPU and

8 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTURE • Notes in numbering operationsWhen performing a numbering operation, set operands in correct

134 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSRL [%ir] Shift right location [ir reg.] logical 2 cyclesFunction:Shifts the content of t

S1C63000 CORE CPU MANUAL EPSON 135CHAPTER 4: INSTRUCTION SETSUB %r,%r’ Subtract r’ reg. from r reg. 1 cycleFunction: r ← r - r’Subtracts the content

136 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSUB %r,[%ir]SUB %r,[%ir]+ Subtract location [ir reg.] from r reg. and increment ir reg.

S1C63000 CORE CPU MANUAL EPSON 137CHAPTER 4: INSTRUCTION SETSUB [%ir],%rSUB [%ir]+,%r Subtract r reg. from location [ir reg.] and increment ir reg.

138 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSUB [%ir],imm4 Subtract immediate data imm4 from location [ir reg.] 2 cyclesFunction: [ir

S1C63000 CORE CPU MANUAL EPSON 139CHAPTER 4: INSTRUCTION SETTST [addr6],imm2XOR %r,%r’ Exclusive OR r’ reg. and r reg. 1 cycleFunction: r ← r ∀ r’Pe

140 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETXOR %r,imm4 Exclusive OR immediate data imm4 and r reg. 1 cycleFunction: r ← r ∀ imm4Perf

S1C63000 CORE CPU MANUAL EPSON 141CHAPTER 4: INSTRUCTION SETXOR %r,[%ir] Exclusive OR location [ir reg.] and r reg. 1 cycleFunction: r ← r ∀ [ir]Perf

142 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETXOR [%ir],%r Exclusive OR r reg. and location [ir reg.] 2 cyclesFunction: [ir] ← [ir] ∀ r

S1C63000 CORE CPU MANUAL EPSON 143CHAPTER 4: INSTRUCTION SETXOR [%ir],imm4 Exclusive OR immediate data imm4 and location [ir reg.] 2 cyclesFunction:

S1C63000 CORE CPU MANUAL EPSON 9CHAPTER 2: ARCHITECTUREThe EXT register maintains the data set previously until new data is written or an initial rese

144 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETIndexADC %r,%r’... 61ADC %r,imm4 ... 61ADC %r,[%ir] ... 62ADC %r,

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10 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTURE • 16-bit data transfer/arithmetic for the index registers X and YThe following six instructi

S1C63000 CORE CPU MANUAL EPSON 11CHAPTER 2: ARCHITECTURE2.2 Program Memory2.2.1 Configuration of program memoryThe S1C63000 can access a maximum 64K-w

12 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTURE2.2.3 Branch instructionsVarious branch instructions are provided for program repeat and subro

S1C63000 CORE CPU MANUAL EPSON 13CHAPTER 2: ARCHITECTURE(2) Instruction with a 4-bit A register data that specifies a relative addressJR %AThis instru

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14 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTUREPC relative jump instructionsProgram memory0000HFFFFHxxxxHxxxxH-127JR sign8xxxxH+1280000HFFF

S1C63000 CORE CPU MANUAL EPSON 15CHAPTER 2: ARCHITECTUREThis instruction permits the extended addressing with the E flag, and the 8-bit relative addre

16 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTURE • Return instructions (RET, RETS, RETD, RETI)A return instruction is used to return from a s

S1C63000 CORE CPU MANUAL EPSON 17CHAPTER 2: ARCHITECTURETOASCII: ;BCD to ASCII conversionLDB %EXT,0x00 ;Sets address 0040HLDB %XL,0x40JR %ARETD 0x30 ;

18 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTURE2.3.2 Addressing for data memoryFor addressing to access the data memory, the index registers

S1C63000 CORE CPU MANUAL EPSON 19CHAPTER 2: ARCHITECTURE • Accessing for addresses 0000H to 003FHData in this area is used for a relative address by

20 EPSON S1C63000 CORE CPU MANUALCHAPTER 2: ARCHITECTUREThe SP1 increment/decrement affects only the 8-bit field shown in Figure 2.3.3.1, and its oper

S1C63000 CORE CPU MANUAL EPSON 21CHAPTER 2: ARCHITECTUREFig. 2.3.3.4 4-bit stack operationThe SP2 increment/decrement affects only the 8-bit field sh

22 EPSON S1C63000 CORE CPU MANUALCHAPTER 3: CPU OPERATIONCHAPTER 3 CPU OPERATIONThis section explains the CPU operations and the operation timings.3.1

S1C63000 CORE CPU MANUAL EPSON 23CHAPTER 3: CPU OPERATION3.3 Data Bus (Data Memory) Control3.3.1 Data bus statusThe S1C63000 output the data bus statu

S1C63 FamilyDevicesS1 C 63158 F 0A01Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP

24 EPSON S1C63000 CORE CPU MANUALCHAPTER 3: CPU OPERATION3.3.3 Interrupt vector readWhen an interrupt is generated, the CPU reads the interrupt vector

S1C63000 CORE CPU MANUAL EPSON 25CHAPTER 3: CPU OPERATION3.3.5 Memory readIn an execution cycle that reads data from the data memory, the read signal

26 EPSON S1C63000 CORE CPU MANUALCHAPTER 3: CPU OPERATIONAfter an initial reset, all the interrupts including NMI are masked until both the stack poin

S1C63000 CORE CPU MANUAL EPSON 27CHAPTER 3: CPU OPERATIONEach of the addresses listed above corresponds to an interrupt factor individually. A branch

28 EPSON S1C63000 CORE CPU MANUALCHAPTER 3: CPU OPERATION3. Instructions that set the stack pointerLDB %SP1,%BA LDB %SP2,%BAThese two instructions are

S1C63000 CORE CPU MANUAL EPSON 29CHAPTER 3: CPU OPERATIONCLKPKPLPCFETCHBS16DBS1/0WRRDRDIVDA00–DA15D0–D3M00–M15IRQIACKNACKIF0 12345DUMMY (010xH) ANYpc-

30 EPSON S1C63000 CORE CPU MANUALCHAPTER 3: CPU OPERATION • Software interruptsThe software interrupts are generated by the INT instruction. Time of

S1C63000 CORE CPU MANUAL EPSON 31CHAPTER 3: CPU OPERATION3.6 Standby StatusThe S1C63000 has a function that stops the CPU operation and it can greatly

32 EPSON S1C63000 CORE CPU MANUALCHAPTER 3: CPU OPERATIONDuring SLEEP status, as in the HALT status, the contents of the registers in the CPU that hav

S1C63000 CORE CPU MANUAL EPSON 33CHAPTER 4: INSTRUCTION SETCHAPTER 4INSTRUCTION SETThe S1C63000 offers high machine cycle efficiency and a high speed

34 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SET • Register direct addressingThe register direct addressing is the addressing mode when sp

S1C63000 CORE CPU MANUAL EPSON 35CHAPTER 4: INSTRUCTION SETThese instructions perform a PC relative branch using the content (4 bits) of a memory spec

36 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETExamples:LDB %EXT,0x15LDB %XL,0x7D ...Works as "LD %X, 0157D"LDB %EXT,0xB8ADD %X

S1C63000 CORE CPU MANUAL EPSON 37CHAPTER 4: INSTRUCTION SET • Signed 16-bit PC relative addressingThe addressing mode of the following branch instruc

38 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SET4.2.2 Symbol meaningsThe following indicates the meanings of the symbols used in the instru

S1C63000 CORE CPU MANUAL EPSON 39CHAPTER 4: INSTRUCTION SETMemory[%X], [X] ... Memory where the X register specifies[%Y], [Y] ...M

40 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SET4.2.3 Instruction list by functionLD %A,%A%A,%B%A,%F%A,imm4%A,[%X]%A,[%X]+%A,[%Y]%A,[%Y]+LD

S1C63000 CORE CPU MANUAL EPSON 41CHAPTER 4: INSTRUCTION SETADD %A,%A%A,%B%A,imm4%A,[%X]%A,[%X]+%A,[%Y]%A,[%Y]+ADD %B,%A%B,%B%B,imm4%B,[%X]%B,[%X]+%B,[

42 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSUB %B,%A%B,%B%B,imm4%B,[%X]%B,[%X]+%B,[%Y]%B,[%Y]+SUB [%X],%A[%X],%B[%X],imm4[%X]+,%A[%X]+

S1C63000 CORE CPU MANUAL EPSON 43CHAPTER 4: INSTRUCTION SETCMP [%X],%A[%X],%B[%X],imm4[%X]+,%A[%X]+,%B[%X]+,imm4CMP [%Y],%A[%Y],%B[%Y],imm4[%Y]+,%A[%Y

S1C63000 CORE CPU MANUAL EPSON iCONTENTSS1C63000 CORE CPU MANUALPREFACEThis manual explains the architecture, operation and instruction of the core CP

44 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETAND %A,%A%A,%B%A,imm4%A,[%X]%A,[%X]+%A,[%Y]%A,[%Y]+AND %B,%A%B,%B%B,imm4%B,[%X]%B,[%X]+%B,[

S1C63000 CORE CPU MANUAL EPSON 45CHAPTER 4: INSTRUCTION SETXOR %A,%A%A,%B%A,imm4%A,[%X]%A,[%X]+%A,[%Y]%A,[%Y]+XOR %B,%A%B,%B%B,imm4%B,[%X]%B,[%X]+%B,[

46 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSLL %A%B[%X][%X]+[%Y][%Y]+SRL %A%B[%X][%X]+[%Y][%Y]+RL %A%B[%X][%X]+[%Y][%Y]+RR %A%B[%X][%X

S1C63000 CORE CPU MANUAL EPSON 47CHAPTER 4: INSTRUCTION SETNote: • The extended addressing (combined with the E flag) is available only for the instru

48 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SET4.2.4 List in alphabetical orderADC %A,%A%A,%B%A,imm4%A,[%X]%A,[%X]+%A,[%Y]%A,[%Y]+%B,%A%B,

S1C63000 CORE CPU MANUAL EPSON 49CHAPTER 4: INSTRUCTION SETADD [%X],imm4[%X]+,%A[%X]+,%B[%X]+,imm4[%Y],%A[%Y],%B[%Y],imm4[%Y]+,%A[%Y]+,%B[%Y]+,imm4AND

50 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETBIT [%Y],imm4[%Y]+,%A[%Y]+,%B[%Y]+,imm4CALR [00addr6]CALR sign8CALZ imm8CLR [00addr6],imm2[

S1C63000 CORE CPU MANUAL EPSON 51CHAPTER 4: INSTRUCTION SETINC [%X],n4[%X]+,n4[%Y],n4[%Y]+,n4[00addr6]INT imm6JP %YJR %A%BAsign8[00addr6]JRC sign8JRNC

52 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETLDB %BA,%YH%BA,%YL%BA,imm8%BA,[%X]+%BA,[%Y]+%EXT,%BA%EXT,imm8%SP1,%BA%SP2,%BA%XH,%BA%XL,%BA

S1C63000 CORE CPU MANUAL EPSON 53CHAPTER 4: INSTRUCTION SETRETIRETSRL %A%B[%X][%X]+[%Y][%Y]+RR %A%B[%X][%X]+[%Y][%Y]+SBC %A,%A%A,%B%A,imm4%A,[%X]%A,[%

ii EPSON S1C63000 CORE CPU MANUALCONTENTS3.5 Interrupts...

54 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETSLL [%X][%X]+[%Y][%Y]+SLPSRL %A%B[%X][%X]+[%Y][%Y]+SUB %A,%A%A,%B%A,imm4%A,[%X]%A,[%X]+%A,[

S1C63000 CORE CPU MANUAL EPSON 55CHAPTER 4: INSTRUCTION SET4.2.5 List of extended addressing instructions↓ –––↓ –––↓ –––↓ –––↓ –––↓ –––↓ –––↓ –––↓ –––

56 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SET↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓

S1C63000 CORE CPU MANUAL EPSON 57CHAPTER 4: INSTRUCTION SET↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ –↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ –

58 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SET↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ ––↓ –

S1C63000 CORE CPU MANUAL EPSON 59CHAPTER 4: INSTRUCTION SET4.3 Instruction FormatsAll the instructions of the S1C63000 are configured with 1 word (13

60 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETAdd with carry r' reg. to r reg. 1 cycleFunction: r ← r + r' + CAdds the content

S1C63000 CORE CPU MANUAL EPSON 61CHAPTER 4: INSTRUCTION SETADC %r,%r'ADC %r,imm4 Add with carry immediate data imm4 to r reg. 1 cycleFunction:

62 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETADC %r,[%ir] Add with carry location [ir reg.] to r reg. 1 cycleFunction: r ← r + [ir] + C

S1C63000 CORE CPU MANUAL EPSON 63CHAPTER 4: INSTRUCTION SETADC [%ir],%r Add with carry r reg. to location [ir reg.] 2 cyclesFunction: [ir] ← [ir] + r

S1C63000 CORE CPU MANUAL EPSON 1CHAPTER 1: OUTLINECHAPTER 1OUTLINEThe S1C63000 is the core CPU of the 4-bit single chip microcomputer S1C63 Family tha

64 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETADC [%ir],imm4ADC [%ir]+,imm4Add with carry immediate data imm4 to location [ir reg.] 2 c

S1C63000 CORE CPU MANUAL EPSON 65CHAPTER 4: INSTRUCTION SETADC %B,%A,n4 Add with carry A reg. to B reg. in specified radix 2 cyclesFunction: B ← N&ap

66 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETADC %B,[%ir]+,n4ADC [%ir],%B,n4 Add with carry B reg. to location [ir reg.] in specified

S1C63000 CORE CPU MANUAL EPSON 67CHAPTER 4: INSTRUCTION SETADC [%ir]+,%B,n4Add with carry B reg. to location [ir reg.] in specified radix and increme

68 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETADC [%ir]+,0,n4ADD %r,%r' Add r' reg. to r reg. 1 cycleFunction: r ← r + r&apos

S1C63000 CORE CPU MANUAL EPSON 69CHAPTER 4: INSTRUCTION SETADD %r,imm4 Add immediate data imm4 to r reg. 1 cycleFunction: r ← r + imm4Adds the 4-bit

70 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETADD %r,[%ir]+ Add location [ir reg.] to r reg. and increment ir reg. 1 cycleFunction: r ←

S1C63000 CORE CPU MANUAL EPSON 71CHAPTER 4: INSTRUCTION SETADD [%ir]+,%r Add r reg. to location [ir reg.] and increment ir reg. 2 cyclesFunction: [ir

72 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETADD [%ir]+,imm4Add immediate data imm4 to location [ir reg.] and increment ir reg. 2 cycle

S1C63000 CORE CPU MANUAL EPSON 73CHAPTER 4: INSTRUCTION SETADD %ir,sign8 Add immediate data sign8 to ir reg. 1 cycleFunction: ir ← ir + sign8Adds the

2 EPSON S1C63000 CORE CPU MANUALCHAPTER 1: OUTLINE1.3 Block DiagramFigure 1.3.1 shows the S1C63000 block diagram.Fig. 1.3.1 S1C63000 block diagram1.4

74 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETAND %r,imm4 Logical AND of immediate data imm4 and r reg. 1 cycleFunction: r ← r ∧ imm4Per

S1C63000 CORE CPU MANUAL EPSON 75CHAPTER 4: INSTRUCTION SETAND %r,[%ir]AND %r,[%ir]+ Logical AND of location [ir reg.] and r reg. and increment ir r

76 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETAND [%ir],%r Logical AND of r reg. and location [ir reg.] 2 cyclesFunction: [ir] ← [ir] ∧ r

S1C63000 CORE CPU MANUAL EPSON 77CHAPTER 4: INSTRUCTION SETAND [%ir],imm4 Logical AND of immediate data imm4 and location [ir reg.] 2 cyclesFunction:

78 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETBIT %r,%r’ Test bit of r reg. with r’ reg. 1 cycleFunction: r ∧ r’Performs a logical AND o

S1C63000 CORE CPU MANUAL EPSON 79CHAPTER 4: INSTRUCTION SETBIT %r,[%ir]BIT %r,[%ir]+ Test bit of r reg. with location [ir reg.] and increment ir reg

80 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETBIT [%ir],%r Test bit of location [ir reg.] with r reg. 1 cycleFunction: [ir] ∧ rPerforms

S1C63000 CORE CPU MANUAL EPSON 81CHAPTER 4: INSTRUCTION SETBIT [%ir],imm4BIT [%ir]+,imm4Test bit of location [ir reg.] with immediate data imm4 and

82 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETCALR [addr6] Call subroutine at relative location [addr6] 2 cyclesFunction: ([(SP1-1)*4+3]

S1C63000 CORE CPU MANUAL EPSON 83CHAPTER 4: INSTRUCTION SETCALZ imm8 Call subroutine at location imm8 1 cycleFunction: ([(SP1-1)*4+3]~[(SP1-1)*4]) ←

S1C63000 CORE CPU MANUAL EPSON 3CHAPTER 1: OUTLINETable 1.4.1(b) Input/output signal list (2)Type I/OII/OI/OOOOIOIIOOOOOOOFunctionTerminal nameData b

84 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETCMP %r,%r’CMP %r,imm4 Compare r reg. with immediate data imm4 1 cycleFunction: r - imm4Su

S1C63000 CORE CPU MANUAL EPSON 85CHAPTER 4: INSTRUCTION SETCMP %r,[%ir]CMP %r,[%ir]+Compare r reg. with location [ir reg.] 1 cycleFunction: r - [ir]

86 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETCMP [%ir],%rCMP [%ir]+,%r Compare location [ir reg.] with r reg. and increment ir reg. 1

S1C63000 CORE CPU MANUAL EPSON 87CHAPTER 4: INSTRUCTION SETCMP [%ir],imm4CMP [%ir]+,imm4Compare location [ir reg.] with immediate data imm4 and incr

88 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETCMP %ir,imm8DEC [addr6]Compare ir reg. with immediate data imm8 1 cycleFunction: ir - imm

S1C63000 CORE CPU MANUAL EPSON 89CHAPTER 4: INSTRUCTION SETDEC [ir],n4 Decrement location [ir] in specified radix 2 cyclesFunction: [ir] ← N’s adjust

90 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETDEC %spEX %A,%B Exchange A reg. and B reg. 1 cycleFunction: A ↔ BExchanges the contents o

S1C63000 CORE CPU MANUAL EPSON 91CHAPTER 4: INSTRUCTION SETEX %r,[%ir] Exchange r reg. and location [ir reg.] 2 cyclesFunction: r ↔ [ir]Exchanges the

92 EPSON S1C63000 CORE CPU MANUALCHAPTER 4: INSTRUCTION SETHALT Set CPU to HALT mode 2 cyclesFunction: HaltSets the CPU to HALT status.The CPU stops o

S1C63000 CORE CPU MANUAL EPSON 93CHAPTER 4: INSTRUCTION SETINC [ir],n4 Increment location [ir] in specified radix 2 cyclesFunction: [ir] ← N’s adjust